A radio system generally includes a transmitter that transmits information-carrying signals to a receiver. The transmitter includes a power amplifier that operates to amplify the signal to be transmitted to a power level that is sufficient to enable receipt of the signal by the receiver. The power amplifier is an active radio frequency sub-system. As such, it is desirable for the power amplifier sub-system to simultaneously achieve both high efficiency and high linearity. However in many applications such as, for example, wireless base station applications, designing power amplifier sub-systems that achieve both high efficiency and high linearity is especially challenging due to high peak to average ratio of the signal due to the use of advanced modulation schemes (e.g., high order Quadrature Amplitude Modulation (QAM), Orthogonal Frequency Division Multiplexing (OFDM), and Code Division Multiple Access (CDMA)) used in current and future wireless communication system standards and the strict requirements on out-of-band emissions imposed by current and future wireless communication system standards.
Adaptive digital predistortion to compensate for the non-linearity of the power amplifier is a proven technology that enables high linearity, high efficiency power amplifier sub-systems. Adaptive digital predistortion requires a feedback path to provide a feedback signal from the output of the power amplifier in order to close the adaptation loop. It is desirable to design the feedback path with minimum cost in terms of hardware and power consumption. However, the predistorted signal exhibits bandwidth expansion on the same order as the distorted signal without predistortion. For instance, if third-order intermodulation distortion (IM3) is the primary distortion to be counteracted, the predistorted signal occupies three times the bandwidth of the original, or input, signal prior to predistortion. Similarly, if fifth-order intermodulation distortion (IM5) is significant and is desired to be counteracted, the predistorted signal occupies five times the bandwidth of the original, or input, signal prior to predistortion. Still further, if higher order intermodulation distortion is desired to be counteracted, the predistorted signal occupies even greater bandwidth.
As the bandwidth of the original, or input, signal prior to predistortion increases, a sampling rate needed to process the predistorted signal approaches or exceeds a clock rate limit that current Integrated Circuit (IC) technology can support. Generally, there are two approaches to address this issue. The first approach is to apply signal processing techniques to support a sampling rate that is higher than the IC clock rate. The second approach is to seek technologies that reduce the required sampling rate. Regarding this second approach, there is a need for systems and methods for reducing the required sampling rate for processing the predistorted signal particularly in the feedback path.